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Edge6435/6436
Per-Pin Electronics Companion DAC
TEST AND MEASUREMENT PRODUCTS Description
The Edge6435/6436 is a low-cost, 40-channel, monolithic ATE level DAC solution manufactured in a wide-voltage bi-CMOS process. The Edge6435/6436 features independent buffered voltage and current outputs that are serially programmed and can be used to provide all of the reference levels required for up to 8 channels of pin electronics in an ATE system. Designated Voltage Output DACs - Wide Voltage Range (16.75V) - Adjustable Full-Scale Range - Adjustable Minimum Offset Voltage - 13-bit Resolution - 11-bit Accuracy (E6436) - 10-bit Accuracy (E6435) Selectable Voltage/Current Output DACs - Wide Voltage/Current Range (16.75V/2 mA) - Adjustable Full-Scale Range - Adjustable Minimum Offset - Configurable as either Voltage or Current Output - 13-bit Resolution - 11-bit Accuracy (E6436) - 10-bit Accuracy (E6435) Designated Current Output DACs - 1.6 mA Range - Adjustable Full-Scale Range - 6-bit Resolution On-chip, digital storage of offset and gain calibration coefficients allow the E6435/6436 output levels to be programmed using "Ideal Code", helping to reduce some of the complexity and time normally associated with programming level DACs in ATE systems. PINCAST allows the Edge6435/6436 to further reduce this complexity and time by allowing channels across multiple Edge6435/6436 devices to be digitally assigned to up to 8 distinct sets that can be addressed and programmed with a limited number of instructions. The Edge6435/6436 features 2 ranks of input latches into each DAC, whereby all DAC values may be updated at one time. For Automated Test Equipment, the Edge6435/6436 can support Pin Electronics and Parametric Measurement Units whose outputs are in the range of -3.25V to +13V, and Driver Super Voltages to +13V after calibration. It provides 10 or 5 per pin levels for 4 or 8 channels respectively. The Edge6435/6436 is designed such that DACs may be shared for various levels whereby minimizing the total number of DACs required in a specific application.
Features
* 40 DACs Partitioned into 4 Groups for 4 or 8 Pin Channels * Wide Voltage Output Range (16.75V Range) * 24 Voltage DACs per Package * 8 Voltage / Current DACs per Package * 8 Current DACs per Package * Adjustable Full-Scale Range and Offset per Group * DUT GND or Analog GND Reference per Group * Self-Calibrating DACs via Internal Offset, Gain Registers * Two Offset, Gain Registers to Support Sharing of DACs * DAC Programming per Channel or Set of Channels * Readback of DAC Input Data and Output Value * Small 100-Pin MQFP Package * Low-Cost, Highly Integrated Multi-DAC Solution
Applications
* Automated Test Equipment (ATE) * Cost Sensitive applications requiring multiple programmable voltage and currents
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Functional Block Diagram
SDIN
CLKIN
4 DAC 0 2 2 2 DACEN 2
Channel 0 VOUTA VOUTB VOUTC IOUTC IOUTD Channel 1 VOUTA VOUTB VOUTC IOUTC IOUTD
UPDATE
4 2 2 2 2
STORE
LOAD 4 RANK 2 2 2 2 Channel 2 VOUTA VOUTB VOUTC IOUTC IOUTD Channel 3 VOUTA VOUTB VOUTC IOUTC IOUTD
RESET*
TESTMODE
4 2 2 2 2 DAC 39
SHIFTOUT*
SDOUT LDOUT
DACOUT
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS PIN Description
Pin Name Power Supplies AVCC AVEE 29, 58, 76 2, 3, 22, 27, 28, 57, 61, 73, 77 21, 26, 60, 74, 96 20, 25, 59, 75, 99 65, 67 64, 68 4, 63, 69 Positive Analog Supply Pins (Output Buffer Supply) Negative Analog Supply Pins Pin # Description
AVDD AGND DVDD DGND VREF Digital I/O Pins CLKIN SDIN
Positive Analog Supply Pins (Core DAC Supply) Analog Supply Ground Pins Digital Supply Input Pins Digital Supply Ground Pins Reference Voltage Input
14 12
Clock input pin. Serial data input pin that is used to read 24-bit words into the E6435 input shift register. Digital input pin that triggers the transfer of data from the serial data input shift register to the central DAC register at up to 33 MHz. Digital input pin that is used to update the rank A latches. Digital input pin that is used to update the rank B latches. Digital input pin that selects either data in the rank A or rank B latches as the DAC input. Digital input pin used to select between "4-channel" or "8-channel" decoding schemes. Digital input pin that is used to initialize the E6435 by placing it into a known state. Digital input pin that is used to set all DAC outputs ~0V (Voltage output DACs) or ~0mA (Current output DACs). Serial data output pin.
LOAD
15
STORE UPDATE RANK
10 9 66
FORMAT
11
RESET* DACEN
7 6
SDOUT Diagnostic Pins TEST_MODE DAC_OUT
17
16 54
Digital input pin that is used to enable/disable the DAC_OUT and LD_OUT functions. High impedance analog voltage output pin that displays the output level of a selected DAC (used for system level diagnostics) when enabled using the TEST_MODE pin. Digital input pin that is used to begin the transmission of serial data through the LD_OUT pin. Serial data output pin used to display the binary value stored in a selected rank A or rank B latch.
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SHIFTOUT*
8
LD_OUT
13
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS PIN Description (continued)
Pin Name 13-Bit Voltage Output DACs VOUTA_0 VOUTA_1 VOUTA_2 VOUTA_3 VOUTA_4 VOUTA_5 VOUTA_6 VOUTA_7 VOUTA_8 VOUTA_9 VOUTA_10 VOUTA_11 VOUTA_12 VOUTA_13 VOUTA_14 VOUTA_15 VOUTB_0 VOUTB_1 VOUTB_2 VOUTB_3 VOUTB_4 VOUTB_5 VOUTB_6 VOUTB_7 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 30 31 32 33 34 35 36 37 Pin # Description
Group A Voltage DAC Output Pins.
Group B Voltage DAC Output Pins.
13_Bit Selectable Voltage/Current Output DACs VOUTC_0 VOUTC_1 VOUTC_2 VOUTC_3 VOUTC_4 VOUTC_5 VOUTC_6 VOUTC_7 IOUTC_0 IOUTC_1 IOUTC_2 IOUTC_3 IOUTC_4 IOUTC_5 IOUTC_6 IOUTC_7 6-Bit Current Output DACs IOUTD_0 IOUTD_1 IOUTD_2 IOUTD_3 IOUTD_4 IOUTD_5 IOUTD_6 IOUTD_7 18 19 1 100 98 97 95 94 38 41 42 45 46 49 50 53 39 40 43 44 47 48 51 52
Group C Voltage DAC Output Pins.
Group C Current DAC Output Pins.
Group D Current DAC Output Pins.
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS PIN Description (continued)
Pin Name Resistor Connections R_MASTER 70 External resistor connection used in combination with R_VGAIN_A, R_VGAIN_B, and R_VGAIN_C to set the maximum output range for the Group A, B, and C voltage output DACs. External Resistor connection used in combination with R_MASTER to set the maximum range for the group A voltage DAC outputs. External Resistor connection used in combination with R_MASTER to set the maximum range for the group B voltage DAC outputs. External Resistor connection used in combination with R_MASTER to set the maximum range for the group C voltage DAC outputs. External resistor connection used to set the base offset voltage for group A voltage DAC outputs. External resistor connection used to set the base offset voltage for group B voltage DAC outputs. External resistor connection used to set the base offset voltage for group C voltage DAC outputs. External resistor connection used to set the maximum range for the group C current DAC outputs. External resistor connection used to set the maximum range for the group D current DAC outputs. Pin # Description
R_VGAIN_A
71
R_VGAIN_B
24
R_VGAIN_C
56
R_OFFSET_A
72
R_OFFSET_B
23
R_OFFSET_C
55
R_IGAIN_C
62
R_IGAIN_D
5
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS PIN Description (continued)
VOUTA_10
VOUTA_11
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
IOUTD_2 AVEE AVEE VREF R_IGAIN_D DACEN RESET* SHIFTOUT* UPDATE STORE FORMAT SDIN LD_OUT CLKIN LOAD TEST_MODE SDOUT IOUTD_0 IOUTD_1 AGND AVDD AVEE R_OFFSET_B R_VGAIN_B AGND AVDD AVEE AVEE AVCC VOUTB_0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
81
VOUTA_12
VOUTA_0
VOUTA_1
VOUTA_2
VOUTA_3
VOUTA_4
VOUTA_5
VOUTA_6
VOUTA_7
VOUTA_8
VOUTA_9
IOUTD_3
IOUTD_4
IOUTD_5
IOUTD_6
IOUTD_7
AGND
AVDD
80 79 78 77 76 75 74 73 72 71
VOUTA_13 VOUTA_14 VOUTA_15 AVEE AVCC AGND AVDD AVEE R_OFFSET_A R_VGAIN_A R_MASTER VREF DGND DVDD RANK DVDD DGND VREF R_IGAIN_C AVEE AVDD AGND AVCC AVEE R_VGAIN_C R_OFFSET_C DAC_OUT VOUTC_7 IOUTC_7 IOUTC_6
Edge6435AHF
100 Lead - 14 x 20 MQFP with Internal Heat Spreader (Top View)
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VOUTB_1
VOUTB_2
VOUTB_3
VOUTB_4
VOUTB_5
VOUTB_6
VOUTB_7
IOUTC_0
IOUTC_1
IOUTC_2
IOUTC_3
IOUTC_4
VOUTC_0
VOUTC_1
VOUTC_2
VOUTC_3
VOUTC_4
IOUTC_5
VOUTC_5
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description
Chip Overview The Edge6435/6436 provides 40 output levels. These outputs can easily be configured to generate the specific analog voltage and current requirements for 4 or 8 channels of ATE pin electronics including: - 3 level driver - Window comparator - Active load - Per pin PMU or PTU without requiring any scaling or shifting via external components. Selection of 4 or 8 channel format is via the FORMAT input. Programming of the chip is done using a 6 wire digital interface comprised of: - Serial Data In - Clock In - Load Grouping of DACs DACs are separated into 4 or 8 channels of 4 distinct functional groups. Groups are defined by: - - - - Type (voltage or current output) Resolution (# of bits) Output range Output compliance.
Table 1 defines the DACs on a per group and channel basis. Group C DACs have both voltage and current output pins. Group C DACs can be individually configured via the serial interface to be either a voltage or current DAC (but not both at the same time). Tables 3 and 4 identify the code needed to configure Group C DACs. Please note that 24 clock cycles are required to load the configuration code for each channel.
Group B 2 per channel 1 per channel V 13 Group C 2 per channel 1 per channel V/I 13 16.75V -3.5V to -0.75V or 2.05 mA (Note 2) yes for Vout no for Iout 200 A(V) -0.2 to +3V(I) Group D 2 per channel 1 per channel I 6
Attribute 4 CH Format Total # of DACs in Group 8 CH Format Type Resolution (# of bits) Output Range: Max DAC Range (Note 1) Offset Range
Group A 4 per channel 2 per channel V 13
16.75V -3.5V to -0.75V
16.75V -3.5V to -0.75V
1.6 mA
Adjustable Output Offset Compliance
yes 200 A
yes 200 A
no -0.2 to +3V
Note 1:
Note 2:
The max DAC range is achieved through specific AVCC, AVEE, and Gain resistor settings. See the equations in the "DAC Voltage Output Overview", "DAC Current Output Overview", and specifications for details. Group C has both voltage and current outputs. Table 1. DAC Grouping
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Voltage Outputs DACs (Groups A, B, C) The output voltage of each E6435/6436 VOUT DAC is a function of external resistor values (R_MASTER, R_VGAIN and R_OFFSET), a reference voltage level (VREF), contents of digital offset and gain registers, and the programmed input code (DATA). The general equation that describes the output voltage as a function of these variables is presented below as Equation 1:
VOUT_[A:C] = 8 * VREF * R_VGAIN_[A:C] R_MASTER CODE 8192 + VOFFSET_[A:C]
Minimum / Maximum Output Voltages See Table 2 for the minimum and maximum possible voltages of a voltage output, where: VOFFSET[A:C] is defined in equation 2, and
VMAX_[A:C]
= 8 * VREF
* R_VGAIN_[A:C] R_MASTER
*
8191 8192
+ VOFFSET_[A:C]
*
Equation 3.
Equation 1.
Resolution The resolution of the DACs in Groups A, B and C is: VRANGE_[A:C] / (213 - 1) where VRANGE_[A:C] is defined in Equation 4. Range The range of the DACs in Groups A, B and C is:
VRANGE_[A:C] = 8 * VREF * R_VGAIN_[A:C] * R_MASTER 8191 8192
where: VOUT[A:C] is the output voltage of a Group A, B, or C Voltage DAC. VREF is an externally applied 2.5V reference voltage R_VGAIN[A:C] is the value of an external resistor used to set the range for Group A, B, or C DACs R_MASTER is the value of an external resistor that sets the bias point/range for the voltage DACs CODE is the base-10 value of the binary code (DATA) loaded into the DAC shift register (see Figures 4 and 5) after it has been modified by the contents of the digitally programmable offset and gain calibration registers as shown in Figure 2. VOFFSET[A:C] is the raw DAC offset voltage that is programmed using an external resistor per group, R_OFFSET[A:C] as follows:
R_OFFSET_[A:C] R_MASTER
Equation 4.
External Resistors Typically computed for R_MASTER = 100k.
VOFFSET_[A:C] = - VREF
DAC Setting MSB ... LSB 0000H
VOUT_[A:C] (V)
VOFFSET_[A:C] VMAX_[A:C]
Equation 2.
1FFFH
As can be seen from Equation 1, the accuracy of the DAC output voltage after calibration is dependent upon the temperature coefficients of VREF and the external resistors.
Table 2. Minimum/Maximum Output Voltages
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Current Output DACs (Groups C, D) Group C DACs The output current of each Group C Current DAC is a function of an external resistor value (R_IGAIN_C), a reference voltage level (VREF), contents of digital offset and gain registers, and the input code (DATA). The general equation that describes the output current as a function of these variables is presented below as Equation 5:
IOUT_C = CODE * 8192 50 x VREF R_IGAIN_C
R_IGAIN_D is the value of an external resistor that sets the output current range for Group D DACs (78.12K R_IGAIN_D 156.25K) DATA is the base-10 value of the binary code loaded into the DAC shift register (see Figures 4 and 5). Functional Description Figure 1 provides a Functional Block Diagram. Figures 2 and 3 show details of the data latches and logic for the DACs. The Edge6435/6436 features a serial data input to program a channel or set of channel's DACs and functions. The Edge6435/6436 also features selfcalibrating DAC outputs via internal offset and gain registers (Figure 2). Figures 4 and 5 show the format of the Serial Input Data for 4 pin channel and 8 pin channel formats. Figure 6 shows the Serial Data Programming Sequence
Equation 5.
where: IOUT_C is the output current of the Group C Current DAC VREF is an externally applied 2.5V reference voltage R_IGAIN_C is the value of an external resistor that sets the output current range for Group C DACs (60.97K R_IGAIN_C 250K) CODE is the base-10 value of the binary code (DATA) loaded into the DAC shift register (see Figures 4 and 5) after it has been modified by the contents of the digitally programmable offset and gain calibraiotn registers as shown in Figure 2. Group D DACs The output current of each group D DAC is a function of an external resistor value (R_IGAIN_D), a reference voltage level (VREF) and the input code (DATA). The general equation that describes the output current as a function of these variables is presented below as Equation 6:
IOUT_D = DATA 64 * 50 x VREF R_IGAIN_D
Tables 3 and 4 provide the Address Maps for 4 pin channel and 8 pin channel formats. FORMAT FORMAT Low selects the 4 pin channel format. FORMAT High selects the 8 pin channel format.
Equation 6.
where: IOUT_D is the output current of the Group D DAC VREF is an externally applied 2.5V reference voltage
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
RESET* RESET* low resets the input shift register (no CLKIN required), the central register, and input registers. With RESET* high, the following leading edge of CLKIN will cause reset condition to be removed (see Figure 21). Two clock cycles are required after RESET* is set to logic "high" for the DAC outputs to be enabled. Programming Sequence The DACs are programmed serially (see Figures 1 and 6). On each rising edge of CLKIN, SDIN is loaded into a shift register. It requires 24 Clocks to fully load the shift register. LOAD Following the serial input of a new DAC value, then LOAD high for the leading edge of CLKIN loads the new DAC value and its address into the Central Register. Following the loading of the Central Register, LOAD needs to go low followed by a leading edge of CLKIN so as to enable the address decoder (see Figure 6). STORE Following the LOAD of the Central Register and the enabling of the address docoder, the channel or set of channels addressed DACs input register or channel function is "stored" by a CLKIN with STORE high. Only upon the STORE of a DAC or set of DAC's "value latch" (Figure 2) does the Edge6435/6436 compute the input to DAC's Latch A (of Rank A). There needs to be at least one clock edge after LOAD is set to logic "low" before STORE is set to logic "high" (see Figure 21). RANK high selects Rank B latches to the DACs (no CLKIN required). DACEN DACEN low forces all DAC voltage outputs to ~0V and all current outputs to ~0 mA (no CLKIN required). With DACEN high, then a following leading edge of CLKIN will cause DACs to be enabled (see Figure 23). TEST MODE/SHIFTOUT* TEST_MODE is used to enable the LDOUT and DACOUT channels. Once enabled (TESTMODE = 1), SHIFTOUT* can be used to begin transmission of serial data through the LDOUT pin, or DAC outputs can be monitored at the DACOUT pin (see Figure 24) (TEST_MODE functionality does not depend on CLKIN)). When addressing DAC channels that have been assigned to a PinCast "set", TEST-MODE is internally disabled in order to prevent multiple DAC outputs from being connected in parallel and possibly damaging the E6435/ 6436. UPDATE Following the STORE of multiple DAC values into Rank A DAC latches, Rank B latches may be updated in parallel with the values of their Rank A DAC latches by a CLKIN with UPDATE high. There must be at least 16 clock cycles between when STORE is set to logic "low" and UPDATE is latched to logic "high" in order to latch the latest data (see Figure 21). RANK Selection Referring to Figures 1, 2 and 3: RANK low selects Rank A latches to the DACs (no CLKIN required).
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Serial Programming The Edge6435/6436 is programmed with 24-bit serial data (Figure 6) in either a 4 channel (Figure 4) or 8 Channel (Figure 5) format. Following the input of serial data, it is loaded into a central register by LOAD (Figure 1). The central register's contents are stored in the "addressed" latch by the STORE input. Tables 3 and 4 show the "Address Maps" for the 4 and 8 channel formats. Referring to Table 3 for 4 channel format, a channel's DACs Set Register or Function may be addressed and the "stored" value changed. For each DAC, there are associated multiple latches (Figures 2 and 3). For the 13-bit DACs (Figure 2) the DAC's output is a function of the contents of its value, gain and offset latches. The Edge6435/6436 features two gain and offset latches per DAC whereby a DAC's output may be shared. For example, in ATE a DAC's value may be shared between a pin driver's high level and a pin's parametric unit's high limit level, where each application requires different offset and gain factors to calibrate each path correctly. Gains and offsets are computed externally to the Edge6435/6436 in the process of pin channel level calibration in the ATE. Gains and offsets are stored in the Edge6435/6436 in the same manner as other latches. Selection of what is stored is determined by the "register selection" bits in the 24-bit input data (Figures 2 and 4). Upon storing a 13-bit DAC's Value, the resultant DAC's ((Value x Gain) + Offset + 4096 Value) is updated by UPDATEA (Figure 2) into the DAC's output latch of RANKA. The contents of all RANKA latches may be transferred to RANKB latches, in parallel, across multiple Edge6435/6436's by the UPDATE input into the Edge6435/6436. The RANK input into the Edge6435/ 6436 selects either RANKA or RANKB latches for all DACs. For the 6-bit DACs (Figure 3) the DAC's output is selected from four "value latches". Referring to Table 3, a channels Set Register may also be programmed. This is an independent 8-bit register per channel which determines the "sets" to which the channel belongs. Figure 7 shows details of programming a channel's Set Register, which is stored in the Edge6435/6436 by the STORE input. A channel may
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belong to none, one, or any combination of up to 8 distinct sets. The address maps show that a channel's DAC (or Function) may be addressed individually, or a DAC (or Function) of multiple channels belonging to the same set may be programmed in parallel. Figure 11 shows an example of addressing channels by sets. Referring to Table 3, a Channel's function is programmed as indicated in Figure 9 (offset and gain selection as well as Group C DAC V/I output selection, see below). Channel's Functions (for 13 bit DACs only), with R2 = R1 = R0 = 0, then: D0 = 0: D0 = 1: D1 = 0: D1 = 1: Selects 1st Offset/Gain Registers Selects 2nd Offset/Gain Registers Selects Voltage Output on Group C DACs Selects Current Output on Group C DACs
Referring to Table 4 for 8 channel format, and Figures 2, 3, 5, 8 and 10, a channel's DACs, Set Registers and Function, etc. are programmed and operate similar to the 4 channel format described above. NOTE: The STORE of a DAC's offset or gain does not result in a DAC output change. Only upon the STORE of a DAC or set of DAC's "value" does the Edge6435/6436 compute the input to DAC's "A" latches. In a tester having multiple Edge6435/6436s, DACs or channel functions may be programmed individually or as a set (1 of 8) of channels across all channels. If multiple E6435/6436s are programmed in parallel, individual DAC or Function programming requires the STORE input to the associated Edge6435/6436 to be applied where all STORE inputs to other Edge6435/6436s are to be inhibited (externally). Programming a DAC or Function of a Set of Channels requires STORE input to be applied to all Edge6435/6436s. Edge6435/6436's DACs may be "updated" in parallel following the programming of DACs as individual DACs or sets of DACs.
Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
STORE
UPDATE
RANK
DACEN
Decode and Individual DAC Update
C R R C C S
R
A DAC0 D DACSEL0
SR4-SR0
D UPDATEA
D
B
VOUTA_0
A D UPDATEA D D B
DAC1
VOUTA_1
DACSEL1
UPDATEB
A FORMAT ADDRESS AND SET DECODERS DISABLE R 11 C R
A3-A0 C1-C0 M1-M0 R2-R0 D12-D0
D7-D0
DAC39 D UPDATEA R 13 R R D D B
IOUTD_3
CENTRAL REGISTER LOAD LCLK RESET
(24 Bits)
LDOUT
CLKIN SDIN RESET* S RESET
24-BIT SHIFT REGISTER
SDOUT
DACOUT
Programming Logic NOTE: VOUT, IOUT names shown for 4 Channel Format. NOTE: Not shown is the function of the Latched Data Readback (via LDOUT) and the DAC Value Readback (via DACOUT). Details of the 'Store' Latches are shown on the following pages.
Figure 1. DAC Functional Block Diagram
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
D[12:0]
STORE 13 D V 13
UPDATEA SEQUENCE GENERATOR
UPDATEA
UPDATE
RANK
DACSEL
SR0 13
A
D[9:0]
D V G SR1 10 10 A
/4096
13
+
13 D D
B
+
D[9:0]
D V G SR2
10
SEL B
R
R
D[9:0]
D O SR3 10 A 10 D O SR4 CALSEL R SEL B 10
D[9:0]
KEY: V: Value Latch that contains DATA programmed to a DAC (see Figures 4 & 5). O: Offset Latches that are used to store offset calibration coefficients (two offset latches per DAC allow the DAC to be shared in a system). G: Gain Latches that are used to store gain calibration coefficients (two gain latches per DAC allow the DAC to be shared in a system). NOTE: CALSEL common to all DACs assigned to a Channel DAC Output (CODE): CODE = V * (G + 4096) 4096 +O
Function R2 0 0 0 0 1
Register Selection R1 0 0 1 1 0 R0 0 1 0 1 0 Select SR0 SR1 SR2 SR3 SR4
DAC Data Gain Register A Gain Register B Offset Register A Offset Register B
Figure 2. Details of DAC Data Latches for 13 Bit DACs (Groups A, B, and C)
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
UPDATEB D[12:7] STORE
RANK
D VA DACSEL SR0
6 A A 6 D B
D VB V SR1
6 B
M U X
D VC V SR2 6 C
R
D VD SR3
6 D
D[8:7] D VS SR4 2
R
KEY: VA, VB, VC, VD: Value Latches A, B, C, D VS: Value Selection Latch
Value Selection (VS) D8 0 0 1 1 D7 0 1 0 1 Select A B C D
Figure 3. Details of DAC Data Latches for 6 Bit DACs (Group D)
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
DATA
ADDRESS
R2
R1
R0
D12 D11 D10 MSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 LSB
M1
M0
C1
C0
A3 MSB
A2
A1
A0 LSB
REGISTER
MODE
CHANNEL
Figure 4. Format of Address and Data in Shift Register (4 Channel Format)
DATA
ADDRESS
R2
R1
R0
D12 D11 D10 MSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 LSB
M1
M0
C1 MSB
C0
A3
A2
A1 LSB
A0 LSB
REGISTER
MODE
CHANNEL
Figure 5. Format of Address and Data in Shift Register (8 Channel Format)
LSB Addr. SDIN A0 A1
MSB Addr. M0 M1
LSB Data D0 D1
MSB Data R1 R2
Next Set of Data A0 A1
CLKIN
CK1
TCK
CK24
LOAD
SDOUT
Previous Data
A0
A1
Corresponds to A0 loaded at CK1
Figure 6. Serial Data Programming Sequence
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
DATA ADDRESS
X
X
X
X MSB
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0 LSB
0
0
C1
C0
1 MSB
1
0
0 LSB
REGISTER
MODE
CHANNEL
Figure 7. Format of Address and Data for Programming to SET REGISTER (4 Channel Format)
DATA
ADDRESS
X
X
X
X MSB
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0 LSB
0
0
C1 MSB
C0
1 MSB
1
0 LSB
A0 LSB
REGISTER
MODE
CHANNEL
Figure 8. Format of Address and Data for Programming to SET REGISTER (8 Channel Format)
DATA
ADDRESS
0
0
0
X MSB
X
X
X
X
X
X
X
X
X
X
D1
D0 LSB
0
0
C1
C0
1 MSB
1
1
0 LSB
REGISTER
MODE
CHANNEL
Figure 9. Format of Address and Data for Programming a Channel's Function (4 Channel Format)
DATA
ADDRESS
0
0
0
X MSB
X
X
X
X
X
X
X
X
X
X
D1
D0 LSB
0
0
C1 MSB
C0
1 MSB
1
1
A0
LSB LSB
REGISTER
MODE
CHANNEL
Figure 10. Format of Address and Data for Programming a Channel's Function (8 Channel Format)
2006 Semtech Corp. / Rev. 3, 8/25/06
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
DATA
ADDRESS
X
X
X
X MSB
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
0
0
C1
C0
1 MSB
1
0
0 LSB
REGISTER STORE
MODE
CHANNEL
0
1
0
1
0
0
0
0
CHANNEL'S SET REGISTER (Channel belongs to Sets 4 and 6)
COM
PAR E
1 of 8 Selection
DATA
ADDRESS
R2
R1
R0
D12 D11 D10 MSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 LSB
M1 LSB
1
C1 MSB
C0
A3 MSB
A2
A1
A0 LSB
Channel Set Selection
If Set 4 is selected, then channel's DAC value or Function will be `stored'. If Set 3 is selected, then the channel will not be `addressed'.
Figure 11. Example of Channel's Set Selection (4 Channel Format)
2006 Semtech Corp. / Rev. 3, 8/25/06
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
FORMAT = 0 Bit # Hex Multiplier Binary Position Item DAC Output Pin Name
VOUTA_0 VOUTA_1 VOUTA_2 VOUTA_3 N/A VOUTB_0 VOUTB_1 VOUTC_0, IOUTC_0 VOUTC_1, IOUTC_1 IOUTD_0 IOUTD_1 N/A N/A N/A 23 22 21 20 19-16 0x10 0000 0x01 0000 8 4 2 1 8- 1 R1 X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X 0 0 0 0 X R0 D12 D11 - D8 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 15-12 0x1000 8- 1 11 8 D3 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 10 9 0x0100 4 2 D2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D1 X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X 0 1 X 8 1 D0 X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X 0 1 X X X 7 8 M1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 4 M0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 2 C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 8 2 4 1 2 A1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 1 A0 0 1 0 1 N/A 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1
Register
R2 X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X 0 0 0 0 X
Data
D7 - D4 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A3 A2 0 0 0 0 0 0 0 0
Group A 13-bit V
Reserved Group B 13-bit V
CHANNEL 0
Group C 13-bit V/I Group D 6-bit I (Note 1) PINCAST Register 0 Reserved Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DACs as Vout Configure Group C DACs as Iout Reserved
N/A N/A
Group A 13-bit V
Reserved Group B 13-bit V
CHANNEL 1
N/A VOUTA_4 VOUTA_5 VOUTA_6 VOUTA_7 N/A VOUTB_2 VOUTB_3 VOUTC_2, IOUTC_2 VOUTC_3, IOUTC_3 IOUTD_2 IOUTD_3 N/A N/A N/A
N/A
N/A
Group C 13-bit V/I
Group D 6-bit I (Note 1) PINCAST Register 1 Reserved Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DACs as Vout Configure Group C DACs as Iout Reserved
CHANNEL FUNCTIONS
N/A N/A
Group A 13-bit V
Reserved Group B 13-bit V
CHANNEL 2
N/A VOUTA_8 VOUTA_9 VOUTA_10 VOUTA_11 N/A VOUTB_4 VOUTB_5 VOUTC_4, IOUTC_4 VOUTC_5, IOUTC_5 IOUTD_4 IOUTD_5 N/A N/A N/A
N/A
N/A
Group C 13-bit V/I
Group D 6-bit I (Note 1) PINCAST Register 2 Reserved Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DACs as Vout Configure Group C DACs as Iout Reserved
N/A N/A
Reserved
N/A VOUTA_12 VOUTA_13 VOUTA_14 VOUTA_15 N/A VOUTB_6 VOUTB_7 VOUTC_6, IOUTC_6 VOUTC_7, IOUTC_7
N/A
N/A
CHANNEL 3
Group D 6-bit I (Note 1) PINCAST Register 3 Reserved Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DACs as Vout Configure Group C DACs as Iout Reserved
IOUTD_6 IOUTD_7 N/A N/A
N/A N/A
N/A
(continued next page)
N/A
Note 1: All 6-bit DACs are programmed with the MSB at the D12 bit position and extending down to D7 for the LSB. D[6:0] bit positions are "don't cares". Table 3. Address Map (4 Channel Format)
2006 Semtech Corp. / Rev. 3, 8/25/06 18 www.semtech.com
Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
FORMAT = 0 Item All DACs
Bit # Hex Multiplier Binary Position DAC Output Pin Name
All DAC Output Pins
23 22 21 20 0x10 0000 842 1
19-16 0x01 0000 8- 1
15-12 0x1000 8- 1
11 8
10 9 0x0100 4 2 D1 X
8 1 D0 X
7 8 M1 1
6 5 0x0010 4 2 M0 0 C1 0
4 1 C0 0
3 8 A3 0
2 4 A2 0
1 2 A1 0
0 1 A0 0
Register
R2 R1 R0 D12 D11 - D8 XXXX X
Data
D7 - D4 X D3 D2 X X
Mode
Address
Parallel Load of All DACs Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB).
VOUTA_0 VOUTA_4 VOUTA_8 VOUTA_12 VOUTA_1 VOUTA_5 VOUTA_9 VOUTA_13 VOUTA_2 VOUTA_6 VOUTA_10 VOUTA_14 VOUTA_3 VOUTA_7 VOUTA_11 VOUTA_15 N/A VOUTB_0 VOUTB_2 VOUTB_4 VOUTB_6 VOUTB_1 VOUTB_3 VOUTB_5 VOUTB_7
VOUTC_0 VOUTC_2 VOUTC_4 VOUTC_6 or IOUTC_0 IOUTC_2 IOUTC_4 IOUTC_6 VOUTC_1 VOUTC_3 VOUTC_5 VOUTC_7 or IOUTC_1 IOUTC_3 IOUTC_5 IOUTC_7
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
0
0
0
0
GROUP A DACs
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
0
0
1
0
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
0
0
1
1
PINCAST SET FUNCTIONS
Reserved
GROUP B DACs
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Parallel Load of denoted VOUTB DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted VOUTB DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted VOUTC or IOUTC DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted VOUTC or IOUTC DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted IOUTD DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted IOUTD DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Reserved
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
0
1
1
0
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
0
1
1
1
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
1
0
0
0
GROUP C DACs
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
1
0
0
1
GROUP D DACs
IOUTD_0 IOUTD_2 IOUTD_4 IOUTD_6 IOUTD_1 IOUTD_3 IOUTD_5 IOUTD_7 N/A
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Table 3. Address Map (4 Channel Format) - cont'd
2006 Semtech Corp. / Rev. 3, 8/25/06
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Bit # Hex Multiplier Binary Position Item
Group A 13-bit V Reserved Group B 13-bit V
CHANNEL 0
23
FORMAT = 1
22 21 20 19-16 0x01 0000 0x10 0000 8 4 2 1 8- 1 R1 X X X X R0 X X X X D12 D11 - D8 X X X X X X X X
15-12 0x1000 8- 1
11 8 D3 X X X X
10 9 0x0100 4 2 D2 X X X X D1 X X X X
8 1 D0 X X X X
7 8
6 4
5 2 C1 0 0 0 0
4 1 C0 0 0 0 0
3 8
2 4
1 2
0 1
DAC Output Pin Name
VOUTA_0 VOUTA_2 N/A VOUTB_0
Register
R2 X X X X
Data
D7 - D4 X X X X M1 M0 0 0 0 0 0 0 0 0 A3 A2 A1 A0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0
N/A -3.5V to +13.75V (16.75V Max Swing)
V: -3.5V to +13.75V
Group C 13-bit V/I Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout Group A 13-bit V Reserved Group B 13-bit V VOUTC_0, IOUTC_0 IOUTD_0 N/A N/A X X X 0 0 0 0 X X X X X X X 0 0 0 0 X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X 0 1 X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 0 1 (16.75V Max Swing) I: 0.5mA to 2.05mA 0.8mA to 1.6mA N/A
VOUTA_1 VOUTA_3 N/A VOUTB_1
N/A -3.5V to +13.75V (16.75V Max Swing)
CHANNEL 1
V: -3.5V to +13.75V
Group C 13-bit V/I Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout Group A 13-bit V Reserved Group B 13-bit V VOUTC_1, IOUTC_1 IOUTD_1 N/A N/A X X X 0 0 0 0 X X X X X X X 0 0 0 0 X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X 0 1 X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 (16.75V Max Swing) I: 0.5mA to 2.05mA 0.8mA to 1.6mA N/A
CHANNEL FUNCTIONS (Channels 0 to 3)
VOUTA_4 VOUTA_6 N/A VOUTB_2
-3.5V to +13.75V (16.75V Max Swing) N/A -3.5V to +13.75V (16.75V Max Swing)
CHANNEL 2
V: -3.5V to +13.75V
Group C 13-bit V/I Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout Group A 13-bit V Reserved Group B 13-bit V VOUTC_2, IOUTC_2 IOUTD_02 N/A N/A X X X 0 0 0 0 X X X X X X X 0 0 0 0 X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X 0 1 X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 0 1 (16.75V Max Swing) I: 0.5mA to 2.05mA 0.8mA to 1.6mA N/A
VOUTA_5 VOUTA_7 N/A VOUTB_3
N/A -3.5V to +13.75V (16.75V Max Swing)
CHANNEL 3
V: -3.5V to +13.75V
Group C 13-bit V/I Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout VOUTC_3, IOUTC_3 IOUTD_3 N/A N/A X X X 0 0 0 0 X X X 0 0 0 0 X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X 0 1 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 (16.75V Max Swing) I: 0.5mA to 2.05mA 0.8mA to 1.6mA N/A
(continued next page)
Note 1: All 6-bit DACs are programmed with the MSB at the D12 bit position and extending down to D7 for the LSB. D[6:0] bit positions are "don't cares". Table 4. Address Map (8 Channel Format)
2006 Semtech Corp. / Rev. 3, 8/25/06
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Bit # Hex Multiplier Binary Position Item
Group A 13-bit V Reserved Group B 13-bit V 23 22 21 20 0x10 0000 8 4 2 1 R1 X X X X X X X 0 0 0 0 X X X X X X X 0 0 0 0 X X X X 19-16 0x01 0000 8- 1 15-12 0x1000 8- 1 11 8 D3 X X X X X X X X X X X X X X X X X X X X X X X X X X 10 9 0x0100 4 2 D2 X X X X X X X X X X X X X X X X X X X X X X X X X X D1 X X X X X X X X X 0 1 X X X X X X X X X 0 1 X X X X 8 1 D0 X X X X X X X 0 1 X X X X X X X X X 0 1 X X X X X X 7 8 6 4 5 2 C1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 3 8 A3 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 2 4 1 2 0 1
FORMAT = 1
DAC Output Pin Name
VOUTA_8 VOUTA_10 N/A VOUTB_4 VOUTC_4, IOUTC_4 IOUTD_4 N/A N/A
Register
R2 X X X X X X X 0 0 0 0 X X X X X X X 0 0 0 0 X X X X R0 D12 D11 - D8 X X X X X X X X X X X X X 0 0 0 0 X X X X X X X 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Data
D7 - D4 X X X X X X X X X X X X X X X X X X X X X X X X X X M1 M0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 A1 A0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0
Group C 13-bit V/I Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout Group A 13-bit V Reserved
N/A -3.5 to +13.75V (16.75V Max Swing) V: -3.5 to +13.75V (16.75V Max Swing) I: 0.5mA to 2.05mA 0.8mA to 1.6mA N/A
CHANNEL 4
VOUTA_9 VOUTA_11 N/A VOUTB_5 VOUTC_5, IOUTC_5 IOUTD_5 N/A N/A
Group B 13-bit V Group C 13-bit V/I Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout Group A 13-bit V Reserved Group B 13-bit V
CHANNEL FUNCTIONS (Channels 4 to 7)
N/A -3.5 to +13.75V (16.75V Max Swing) V: -3.5 to +13.75V (16.75V Max Swing) I: 0.5mA to 2.05mA 0.8mA to 1.6mA N/A
CHANNEL 5
VOUTA_12 VOUTA_14 N/A VOUTB_6
CHANNEL 6
-3.5 to +13.75V (16.75V Max Swing) N/A -3.5 to +13.75V (16.75V Max Swing)
Group C 13-bit V/I
VOUTC_6, IOUTC_6
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
0
0
0
V: -3.5 to +13.75V (16.75V Max Swing) I: 0.5mA to 2.05mA
0.8mA to 1.6mA N/A
Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout Group A 13-bit V
IOUTD_6 N/A N/A
VOUTA_13 VOUTA_15
X X 0 0 0 0 X X
X X 0 0 0 0 X X
X X 0 0 0 0 X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X 0 1 X X
X X 0 1 X X X X
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 0 0
0 1 1 1 1 1 0 0
1 0 1 1 1 1 0 1
Reserved
Group B 13-bit V
N/A
VOUTB_7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0 0 0 0 0 0 1 1 0 1
CHANNEL 7
N/A -3.5 to +13.75V (16.75V Max Swing)
Group C 13-bit V/I
VOUTC_7, IOUTC_7
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
0
0
1
V: -3.5 to +13.75V (16.75V Max Swing) I: 0.5mA to 2.05mA
0.8mA to 1.6mA N/A
Group D 6-bit I (Note 1) PINCAST Register 0 Select Rank 1 Calibration Registers Select Rank 2 Calibration Registers Configure Group C DAC as Vout Configure Group C DAC as Iout
IOUTD_7 N/A N/A
X X 0 0 0 0
X X 0 0 0 0
X X 0 0 0 0
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X 0 1
X X 0 1 X X
0 0 0 0 0 0
0 0 0 0 0 0
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
0 1 1 1 1 1
1 0 1 1 1 1
1 1 1 1 1 1
(continued next page)
Note 1: All 6-bit DACs are programmed with the MSB at the D12 bit position and extending down to D7 for the LSB. D[6:0] bit positions are "don't cares". Table 4. Address Map (8 Channel Format) - cont'd
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
FORMAT = 1
Bit # Hex Multiplier Binary Position Item DAC Output Pin Name
All DAC Output Pins
VOUTA_0 VOUTA_1 VOUTA_4 VOUTA_5 VOUTA_8 VOUTA_9 VOUTA_12 VOUTA_13 VOUTA_2 VOUTA_3 VOUTA_6 VOUTA_7 VOUTA_10 VOUTA_11 VOUTA_14 VOUTA_15 VOUTB_0 VOUTB_1 VOUTB_2 VOUTB_3 VOUTB_4 VOUTB_5 VOUTB_6 VOUTB_7 VOUTC_0 VOUTC_1 VOUTC_2 VOUTC_3 VOUTC_4 VOUTC_5 VOUTC_6 VOUTC_7 or IOUTC_0 IOUTC_1 IOUTC_2 IOUTC_3 IOUTC_4 IOUTC_5 IOUTC_6 IOUTC_7 IOUTD_0 IOUTD_1 IOUTD_2 IOUTD_3 IOUTD_4 IOUTD_5 IOUTD_6 IOUTD_7
23
22 21 20 0x10 0000 8 4 2 1 R1 R0 X X
19-16 0x01 0000 8- 1
15-12 0x1000 8- 1
11 8 D3 X
10 9 0x0100 4 2 D2 X D1 X
8 1 D0 X
7 8 M1 1
6 4 M0 0
5 2 C1 0
4 1 C0 0
3 8 A3 0
2 4 A2 0
1 2 A1 0
0 1 A0 X
Register
R2 X D12 D11 - D8 X X
Data
D7 - D4 X
All DACs
Parallel Load of All DACs Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB).
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
0
0
0
X
GROUP A DACs
Parallel Load of denoted VOUTA DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB).
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
0
0
1
X
PINCAST SET FUNCTIONS
Parallel Load of denoted VOUTB DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB) across multiple E6435 devices.
GROUP B DACs
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
0
1
1
X
GROUP C DACs
Parallel Load of denoted VOUTC or IOUTC DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB).
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
1
0
0
X
GROUP D DACs
Parallel Load of denoted IOUTD DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB).
X
X
X
X
X
X
X
X
X
X
PS0
1
PS2 PS1
1
0
1
X
Table 4. Address Map (8 Channel Format) - cont'd
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Digital Inputs All digital inputs are LV_TTL compatible inputs. Digital Outputs SDOUT and LDOUT are CMOS outputs that switch between DGND and DVDD. Power Supply Sequence Power supplies must be controlled such that they maintain correct polarity with respect to each other and ground at all times during power-up and power-down. The following sequence is recommended: 1. 2. 3. 4. AVEE AVCC AVDD, VREF DVDD DAC Value Readback via DAC_OUT Voltage Outputs Each voltage output of the Edge6435/6436 has high impedance FET(s) connected from the outputs to a common analog line, DAC_OUT, that provides readback of each DAC's value. The primary purpose of this feature is to provide means for diagnostics of correct DAC functionality in an application that can monitor DAC_OUT, and is not intended for DAC calibration. The feature utilizes the normal address decoding, as shown in Tables 3 and 4, as well as a "high" level on the TEST_MODE pin (see truth table below).
TEST_MODE 0 1 DAC_OUT Off On
NOTE: A CLK input is not required to change the state of the DAC_OUT pin when TEST_MODE is toggled.
VOUT_CH0_1
VOUT_CH0_2 TEST_MODE
VOUT_CH0_3
To test an output, a DAC should be loaded as described above. At this point, the DAC_OUT pin, which is an analog output, will reflect the voltage at the addressed DAC's output pin. Note that DAC_OUT is switched off when the parallel load is selected (address 64). This prevents a parallel connection of all the DAC outputs when the scan feature is used.
Address Decoder
DAC_OUT
Figure 12. DAC Voltage Output via DAC_OUT
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Current Outputs The TEST_MODE and DAC_OUT pins on the Edge6435/ 6436 are used in the same way as for voltage outputs. The scan circuits for current outputs are shown in Figure 13. The voltage measured at the DAC_OUT pin, using the configuration in Figure 13, for Group C and D current outputs are as follows: VDAC_OUT_C = (RSENSE_C + RPAD) * IOUT_C where: RSENSE_C = 160 30% RPAD = 30 30% and VDAC_OUT_D = (RSENSE_D + RPAD) * IOUT_D 2) where: RSENSE_D = 160 30% RPAD = 30 30% The typical "ON" resistance of the FET switch is 2 k, but can vary from 900 to 3 k as a function of process and output voltage. Notes when Using DAC_OUT Feature with Multiple Chips When multiple 6435/6436s are used on a board, and it is desired to gang the DAC_OUT pins of these 6435/6436s, or gang the TEST_MODE inputs to one point, it is required to protect the 6435/6436s against damage that the following rules be followed: 1) If TEST_MODE inputs are ganged together, DAC_OUT cannot be ganged, or invalid results will be observed at the DAC_OUT pin and damage could occur to the device. Hence, each DAC_OUT pin on a 6435/6436 will have to be measured separately. If DAC_OUT is ganged, the TEST_MODE is used to select only one DAC at a time.
+
IDAC
R SENSE
R PAD
IOUT_CH0_0
CONNECT TO VIRTUAL GROUND
-
TEST_MODE IDAC
+ -
R SENSE
R PAD
IOUT_CH0_1
CONNECT TO VIRTUAL GROUND
ADDRESS DECODER
+
IDAC
R SENSE
R PAD
IOUT_CH0_2
CONNECT TO VIRTUAL GROUND
-
DAC_OUT
NOTE: WHEN ADDRESS 64 IS INVOKED (PARALLEL LOAD), SCAN IS DISABLED.
Figure 13. DAC Current Output vs DAC_OUT
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Latched Data readback via LD_OUT Figure 14 provides a Functional Block Diagram of the means to readback, via LD_OUT, the status of latch's input into a selected DAC. A DAC's latches are addressed for readback in the same way they are addressed to be written via the serial input, SDIN. A DACs Rank A or Rank B latches are selcted by the RANK input for subsequent readback. Readback is enabled internally by TESTMODE high whereupon the selected DAC's Rank A or Rank B latch outputs are loaded into the READBACK REGISTER by a leading edge of CLKIN while SHIFTOUT* is high. With SHIFTOUT* low, subsequent clocks into CLKIN will shift out, via LD_OUT, the status of the selected DAC's latches of Rank A or Rank B.
TESTMODE
RANK
13 D DACSEL D
A SEL B
DAC
R
R
13
READBACK REGISTER
D C 1 C
SHIFTOUT*
LD_OUT R
Figure 14. Latched Data Readback Functional Block Diagram
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Application Information
Typical Supplies
0V
+10.0V
+5V
+3.3V
0V
-5V
0V
2.5V AGND
SGND
AVCC
AVDD
DVDD
AGND
AVEE
DGND
VREF
VOUT
RANK
10 K
. . . DAC Voltage Outputs . . .
DACEN
10 K
Edge6435
VOUT
RESET*
IOUT . . . DAC Current Outputs . . . IOUT
10 K
R_OFFSET_B
R_VGAIN_B
R_OFFSET_C
R_OFFSET_A
R_VGAIN_C
R_VGAIN_A
IREF GND connect to the same ground as AGND pins or may be connected to DUT GND (via switchable buffer) on a per group basis.
IREF
IREF
IREF
IREF
IREF
IREF
IREF
IREF
R_MASTER
GND
For Group A DACs Gain and Offset Control
For Group B DACs Gain and Offset Control
The Selection of R_MASTER Establishes IREF
For Group C DACs Gain and Offset Control (Voltage)
NOTE: Pull-down resistors required on RANK, DACEN, and RESET* to ensure they are low upon power-up. Such resistors may be common to multiple Edge6435s. NOTE: Power Supply inputs AVCC, AVDD, DVDD and AVEE need bypass capacitors located at the inputs to the chip of 10 F (tant.) and 0.1 F (ceramic).
Figure 15. Required External Components
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R_IGAIN_D
R_IGAIN_C
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
The E6435/E6436 can be configured to provide all of the DAC levels required for 4 fully-featured high-speed pin channels or 8 fully-featured low-speed pin channels when used with other Semtech pin electronics components. Since each E6435/E6436 DAC channel includes 2 sets of calibration registers, DAC channels can be shared across two distinct functions in an application to minimize the overall number of level DACs required in a system. Tables 5 and 6 show the recommended shorting scheme for a couple of possible pin electronics solutions. High-Speed Pin Electronics Solution: 1 - E6435/E6436 per 4 Channels 2 - E7725 Dual Channel, High Speed Pin Driver + Comparator + Load + Signal Clamp devices per 4 Channels 2 - E42X7 Dual-Channel, Parametric Measurement Unit + Clamps per 4 Channels
E6435/6436 Group A A A A B B C C C C D D V/I V V V V V V V V I I I I Function Driver "High" Level Driver "Low Level Upper Voltage Clamp Lower Voltage Clamp Comparator Threshold Comparator Threshold Termination Voltage Not used Load Source Current Load Sink Current Driver "+" Slew Rate Adjust Driver "-" Slew Rate Adjust E7725 Symbol DVH DVL VCH VCL CVA, CVC CVB DVT, VCM N/A ISC ISK RADJ FADJ Function Not used Not used Upper Voltage Clamp Lower Voltage Clamp Lower Comparator Threshold Upper Comparator Threshold Not used Voltage/Current Programming Not used Not used Not used Not used E42X7 Symbol N/A N/A HLV LLV IVMIN IVMAX N/A VINP N/A N/A N/A N/A
Channel 0
E7725
Channel 1
E6435/ E6436
E42X7
E42X7
Channel 2
E7725
Channel 3
Table 5. E6435/E6436 Per-Channel DAC Connectivity for High-Speed Pin Driver, Comparator, Clamp and Load Solution Featuring Differential Capability and Fast Settling PMU Per Pin
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
Channel 0
Low-Speed Pin Electronics Solution: 1 - E6435/E6436 per 8 Channels 2 - E7804 Quad Channel, Driver + Comparator + CTC per 8 Channels devices per 4 Channels 4 - E42X7 Dual-Channel, Parametric Measurement Unit + Clamps per 8 Channels
E6435/ E6436
E7804
Channel 1 Channel 2 Channel 3
E42X7
E42X7
E42X7
E42X7
Channel 4
E7804
Channel 5 Channel 6 Channel 7
E6435/6436 Group A A B C D(0)* D(1)* D(2)* D(3-7)* V/I V V V V I I I I Interconnect Circuit None required None required None required None required I to V Converter I to V Converter I to V Converter None required Function Driver "High" Level Driver "Low" Level
E7804 Symbol DVH DVL CVA CVB CTCFIV CTCLV PVP N/A Function
E42X7 Symbol VINP IVMIN IVMAX HLV LLV N/A N/A N/A
Voltage/Current Programming Comparator Threshold Comparator Threshold Upper Voltage Clamp Lower Voltage Clamp Not used Not used Not used
Comparator Threshold Comparator Threshold Continuity Test Circuit Continuity Test Voltage Pull-up Voltage Not used
*D(0), D(1), D(n) correspond to DAC channels that are used for common continuity test voltage/current programming values across multiple E7804 devices and are shared with the lower voltage clamp threshold on the E42X7. Table 6. E6435/E6436 Per-Channel DAC Connectivity for Low-Speed Pin Driver, Comparator, Continuity Test Circuit, and Per-Pin PMU Solution
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Package Information
Figure 16. 14 x 20 x 2.0 mm, 100-Pin MQFP (with Internal Heat Spreader, Requires Heat Sink)
N
PIN Descriptions
1
.30 RAD. TYP .
.20 RAD. TYP .
1
-A- -B-
D1
D
STANDOFF
A
A1
.25 SEATING PLANE
.17 MAX
L
b
ddd M C A-B S D S
-C-
LEAD COPLANARITY
ccc C
-D-
E1 E
BODY + 3.2mm FOOTPRINT, 2.0mm THICK DIMS. TOLS. Max. Max. .10 .20 .10 .20 .10 0.15 Basic 2.35 .25 2.00 23.20 20.00 17.20 14.00 .88 .65 0.24~0.38 0 - 7 .4 Nom. Max 6 .12 .10
10 Typ.
A A1
A2
A e
A1
A2 D D1 E E1 L e b
10 Typ.
Notes: 1. All dimensions in millimeters (mm). 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length "L" is measured at gage plane 0.25mm above the seating plane. 4. Use MS-022 variation GA-1 for body dimensions. 5. Use MO-112 variation CA-1 for body dimensions. 6. Use variation GA-1 for lead form options and BB for body dime. 7. Use variation GB-1 for lead form options and BB for body dime. 8. Use variation GC-1 for lead form options and BB for body dime. 9. Use MS-022 variation BB for body dimensions. 10. N.J.R. means no single JEDEC reference putline or standard.
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1
ddd ccc JEDEC Ref. Dwg. Variation Designator
Note 8
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Recommended Operating Conditions
Parameter Positive Analog Power Supply Positive Analog Power Supply 2 Negative Power Supply 1 Reference Voltage Total Analog Supply 1 Digital Power Supply Digital Ground Thermal Resistance of Package Junction to Case Junction to Ambient Still Air 100 lfpm 400 lfpm Case Temperature Symbol AVCC AVDD AVEE VREF AVCC - AVEE DVDD - DGND DGND JC JA Min +8.0 +4.75 -5.25 2.499 12.75 3.0 -0.5 0 12.4 28 25.2 22.1 TCASE 25 65 Typ +10.0 +5.0 -5.0 Max +15.0 +5.25 -4.75 2.501 20.25 +5.25 +0.5 Units V V V V V V V C/W C/W C/W C/W C
NOTE: All supplies are referenced to AGND unless otherwise noted.
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Absolute Maximum Ratings
Parameter Positive Analog Supply Positive Analog Supply 2 Negative Analog Supply Digital Power Supply Total Power Supply Symbol AVCC AVDD AVEE DVDD AVCC - AVEE AVCC -AVDD AGND AGND AGND VREF Min -0.5 -5.5 -0.5 -0.5 -0.5 -0.5 -5.5 -0.5 AGND - 0.5 Max +16 +5.5 +0.5 +5.5 +21.5 +16.0 +5.5 +0.5 +0.5 AVDD + 0.5 Units V V V V V V V V V V
Digital Input Voltages DVDD < 5.0V DVDD > 5.0V
SDIN, CLKIN, LOAD, STORE, UPDATE, SELVIC, RANK, RESET* VREF[1:4], VMASTER, VOFFSET_[A:C], VGAIN_[A:C] IGAIN_[C:D] IMASTER VOUT_[A:C] IOUT_[A:C] TA TS TJ TSOL
DGND - 0.5 DGND - 0.5 AGND - 0.5 -100 -100 AVEE - 0.5 -300 0 -65
DVDD + 0.5 +5.5 AVDD + 0.5 +100 +100 AVCC + 0.5 +300 +125 +150 +125 +260
V V V A A V A C C C C
Analog Input Voltages
Analog Input Currents Analog Output Voltages Groups A, B, C Analog Output Currents Groups A, B, C Continuous DC Current Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, .25" from the pin)
NOTE: All supplies are referenced to AGND unless otherwise noted.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS DC Characteristics
Parameter Digital Inputs (SDIN, CLKIN, LOAD, STORE, UPDATE, RANK, RESET*, TESTMODE, DACEN, FORMAT) Input Low Voltage Input High Voltage 3.0V DVDD 3.3V 3.3V < DVDD 5.25V Input Current Digital Outputs (SDOUT, LDOUT) Output Low Voltage Output High Voltage Output Current Low Output Current High DAC Voltage Outputs Groups A, B, and C (Voltage Outputs) Resolution Output Voltage Range Output Voltage Span Output Offset Range Output Current Compliance Range Error (Figure 17) Offset Error (Figure 17) Integral Linearity Error following 2-Point Calibration 20% - 80% Calibration Points (Figure 18) E6436 DACs E6435 DACs Endpoint Calibration Points (Figure 19) E6436 DACs E6435 DACs Integral Linearity Error following 7-Point Calibration (Calibration Points: 0, 1365, 2730, 4095, 5460, 6825, 8191) Differential Linearity Error (Figure 19) Gain TempCo Offset Error TempCo DAC Disabled Output Voltage (DACEN = 0) DAC Interaction (DC Channel-to-Channel Crosstalk) -100 -1 INL VOUT_RANGE VOUT_SPAN VOFFSET ICOMPLIANCE FS_ERROR VOS 13 AVEE + 1.25 8.0 -3.5 -200 -215 -35 AVCC - 1.25 16.75 -0.75 +200 +215 +35 Bits V V V A mV mV Symbol Min Typ Max Units
VIL VIH 2.0 2.6 -1
0.8
V V V A V V mA mA
IIL, IIH VOL VOH IOL IOH
1 0.4 DVDD 1.6
2.4 -0.4
-4 -8 -4 -8 -2
+4 +8 +4 +8 2
LSB LSB LSB LSB LSB
DNL
-1 250 250
+1
LSB V/C V/C
+100 +1
mV mV
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
Parameter Group C (Current Outputs) Resolution Output Current Range Output Voltage Compliance Integral Linearity Error following Calibration (Figure 18) 20% - 80% Calibration Points (Figure 18) Endpoint Calibration Points (Figure 19) Diffrential Linearity Error (Figure 19) Range Error (Figure 17) Offset Error (Figure 17) Gain TempCo Offset Error TempCo DAC Disabled Output Current Group D (Current Outputs) Resolution Output Current Range Output Voltage Compliance Integral Linearity Error following Calibration (Figure 18) 20% - 80% Calibration Points (Figure 18) Endpoint Calibration Points (Figure 19) Differential Linearity Error (Figure 20) Range Error (Figure 17) Offset Error (Figure 17) Gain TempCo Offset Error TempCo DAC Disabled Output Current -20 IOS INL -0.075 -0.075 DNL -0.025 -70 -20 0 50 30 0 +20 +0.075 +0.075 +0.025 +70 20 LSB LSB LSB A A pA/C pA/C A IOUT -20 6 0.8 -0.2 1.6 3.0 IOS INL -7 -7 DNL -1 -70 -20 -130 30 0 +20 +7 +7 1 +70 + 20 LSB LSB LSB A A pA/C pA/C A Bits mA V IOUT Symbol Min 13 0.5 -0.2 2.05 3.0 Typ Max Units Bits mA V
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
DAC Output (Voltage or Current)
Maximum Range
Range Error = Deviation of Real DAC Output from Ideal DAC Output at Max Code
Min Code
ID EA L
Real Transfer Characteristic is somewhere between "dotted" lines
Max Code DAC Code
Minimum Range
Offset Error = Deviation of Real DAC from Ideal DAC at Min Code
Range error and offset error are due to E6435/6436 only. External resistor tolerances and VREF tolerance not included.
Figure 17. Representation of DAC Offset Error and Range Error for 13-Bit DACs (6-bit DACs similar)
DAC Output (Voltage or Current)
Maximum Range
Min Code
St ra igh
tl
in e
th ro ug h2 0
%
an d
80 %
Po in ts
Measured DAC output at 80% of Max Code
Max Code DAC Code
DAC Integral Non-Linearity (INL) Measured DAC Output at 20% of Max Code
Minimum Range
Figure 18. Representation of 2-Point DAC Integral Non-Linearity (INL)
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
DAC Output (Voltage or Current)
Maximum Range
Measured DAC output at Max Code
nt s
Min Code
St ra i
gh
tl
in e
th ro u
gh
En
d
Po i
DAC Integral Non-Linearity (INL)
Max Code DAC Code
Measured DAC Output at Min Code
Minimum Range
Figure 19. Representation of 2-Point DAC Integral Non-Linearity (INL)
DAC Output (LSB)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 DAC Code Measured DAC output must not change by more than DNL specification limits between adjacent DAC codes across the entire DAC range
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
Figure 20. Representation of Differential Non-Linearity (DNL)
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n+14
Edge6435/6436
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
Power Supplies
Parameter Power Supply Consumption (Note 1) Positive Analog Supply (AVCC) Positive Analog Supply (AVDD) Digital Supply (DVDD) 3.0V DVDD 3.3V 3.3V < DVDD 5.25V Negative Power Supply (AVEE) Reference Supply ICC IADD IDDD 250 IEE IREF -50 -0.2 -30 +0.2 500 800 A A mA A 15 20 20 30 mA mA Symbol Min Typ Max Units
Note 1:
CLKIN Low, quiescent.
Parameter Power Supply Rejection Ratio AVCC to any DAC Output DC 100 kHz 500 kHz 1 MHz AVEE to any DAC Output DC 100 kHz 500 kHz 1 MHz AVDD to any DAC Output DC 100 kHz 500 kHz 1 MHz
Symbol PSRR
Min
Typ
Max
Units
-88 -27 -20 -18 -66 -8 -5 -13
dB dB dB dB dB dB dB dB dB dB dB dB
-62
-3 -18 -26
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS AC Characteristics
Parameter Digital Inputs Set Up Times (to CLKIN rising edge) SDIN LOAD STORE UPDATE RESET* DACEN SHIFTOUT* Hold Times SDIN (to CLKIN rising edge) LOAD STORE UPDATE SHIFTOUT* Output Times (to CLKIN Rising Edge) SDOUT LDOUT CLKIN Fmax DVDD = 3.0V to 3.3V DVDD = 4.75V to 5.25V Clock Spacing Clock Width RESET Pulse Width DAC Output Settling Time (Note 2) Full-Scale Step (DAC Code 0 to 8191) Voltage DACs (Groups A, B, C) 16V Range Settling to Specified Linearity Error Settling to 0.5% FSR 8V Range Settling to Specified Linearity Error Settling to 0.5% FSR Current DACs Grroup C Settling to Specified Linearity Error Settling to 0.5% FSR Grroup D (Full-Scale Step, DAC Code 0 to 63) Settling to Specified Linearity Error Settling to 0.5% FSR DAC_OUT Readback Time (Note 1) Voltage DAC Output Enable Time (Note 4) Voltage DAC Output Disable Time (Note 5) Current DAC Output Enable Time (Note 4) Current DAC Output Disable Time (Note 6) Rank Transition Time (Note 3) Vtoe Vtz Itoe Itz Trank 2.3 THLD_SDI THLD_LD THLD_STR THLD_UPD THLD_SOUT TO_SDOUT TO_LDOUT 2 2 2 2 2 ns ns ns ns ns TSU_SDI TSU_LD TSU_STR TSU_UPD TSU_RST TSU_DEN TSU_SOUT 2 2 2 2 2 2 2 ns ns ns ns ns ns ns Symbol Min Typ Max Units
18 18
ns ns
Fmax 60 80 CS_CK CW_CK PWRESET 5 5 3 MHz MHz ns ns ns
Vsettle 65 50 30 30 s s s s
45 35 40 30 5 4 18 1.5 7 1.5
s s s s s s s s s s
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Edge6435/6436
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: DAC_OUT Readback Time is the amount of time required for DAC_OUT to display a valid voltage for a selected (and fully settled) DAC channel and only includes channel-to-channel switching time. Measured from CLKIN using edge of update to specified accuracy. Rank Transition Time is a measurement of the time required to change between Rank A and Rank B latches and does not include DAC Output Settling time. DAC Output Enable Time is measured after DACEN is transitioned from 0 to 1 from the rising edge of the clock signal applied to CLKIN as the time required for the DAC output to change by 10%. Voltage DAC output disable time is measured from the falling edge of DACEN as the amount of time required for the DAC output to change from positive full-scale to 0.5V. Current DAC Output Disable Time is measured from the falling edge of DACEN as the amount of time required for the DAC output to change by 10%.
C
CLKIN TSU_LD
CK24 THLD_LD
LOAD 3C
TSU_STR THLD_STR
16C
2C
STORE TSU_STR
UPDATEA (Internal)
TSU_UPD THLD_UPD
UPDATE _ _ _ _ _ _ _
TSU_UPD
RANK _ _ _ _ _ _ _ _
TSU_RNK THLD_RNK TSU_RNK THLD_RNK
Figure 21. Individual DAC Storing and DAC Updating (RESET* high)
SDIN
Valid Data A0 TSU_SDI
TSU_SDI
Valid Data R2
CKIN
Previous A0 A1
THLD_SDI
THLD_SDI
CK1
TO_SDOUT
CK24
SDOUT
Figure 22. Shift Register Loading Timing Diagram
2006 Semtech Corp. / Rev. 3, 8/25/06
38
www.semtech.com
Edge6435/6436
TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued)
CLKIN TSU_RST TSU_DEN
RESET* DACEN
Figure 23. RESET* and DACEN Timing
STORE or UPDATE
1C
RANK, TESTMODE
> 0 ns
LOAD 1C
CLKIN TSU_SOUT THLD_SOUT TSU_SOUT SHIFTOUT* TO_LDOUT LDOUT
D0 D1
Figure 24. SHIFTOUT*, LDOUT Timing
2006 Semtech Corp. / Rev. 3, 8/25/06
39
www.semtech.com
Edge6435/6436
TEST AND MEASUREMENT PRODUCTS Ordering Information
Model Number E6435BHFT EVM6435
Package 14 x 20 x 2 mm, 100 Pin MQFP (with Internal Heat Spreader) Edge6435 Evaluation Board 14 x 20 x 2 mm, 100 Pin MQFP (with Internal Heat Spreader) Edge6436 Evaluation Board
E6436BHFT
EVM6436
Pb
This product is lead-free.
Contact Information
Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633
2006 Semtech Corp. / Rev. 3, 8/25/06 40 www.semtech.com

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